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1/11 april 2001 n high speed: f max = 190mhz (typ.) at v cc = 5v n low power dissipation: i cc = 4 m a (max.) at t a =25c n compatible with ttl outputs v ih = 2v (min.), v il = 0.8v (max.) n 50 w transmission line driving capability n symmetrical output impedance: |i oh | = i ol = 24ma (min) n balanced propagation delays: t plh @ t phl n operating voltage range: v cc (opr) = 4.5v to 5.5v n pin and function compatible with 74 series 273 n improved latch-up immunity description the 74act273 is an advanced high-speed cmos octal d-type flip flop with clear fabricated with sub-micron silicon gate and double-layer metal wiring c 2 mos technology. information signals applied to d inputs are transfered to the q output on the positive-going edge of the clock pulse. when the clear input is held low, the q outputs are held low independentely of the other inputs. the device is designed to interface directly high speed cmos systems with ttl, nmos and cmos output voltage levels. all inputs and outputs are equipped with protection circuits against static discharge, giving them 2kv esd immunity and transient excess voltage. 74act273 octal d-type flip flop with clear pin connection and iec logic symbols order codes package tube t & r dip 74act273b sop 74act273m 74act273mtr tssop 74ACT273TTR tssop dip sop
74act273 2/11 input and output equivalent circuit pin description truth table x : dont care logic diagram this logic diagram has not be used to estimate propagation delays pin no symbol name and function 1 clear asyncronous master reset (active low) 2, 5, 6, 9, 12, 15, 16,19 q0 to q7 flip-flop outputs 3, 4, 7, 8, 13, 14, 17, 18 d0 to d7 data inputs 11 clock clock input (low-to-high edge triggered) 10 gnd ground (0v) 20 v cc positive supply voltage inputs output function clear d clock q l x x l clear hl l hh h hx q n no change
74act273 3/11 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditi ons is not implied. recommended operating conditions 1) v in from 0.8v to 2.0v symbol parameter value unit v cc supply voltage -0.5 to +7 v v i dc input voltage -0.5 to v cc + 0.5 v v o dc output voltage -0.5 to v cc + 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 20 ma i o dc output current 50 ma i cc or i gnd dc v cc or ground current 400 ma t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage 4.5 to 5.5 v v i input voltage 0 to v cc v v o output voltage 0 to v cc v t op operating temperature -55 to 125 c dt/dv input rise and fall time v cc = 4.5 to 5.5v (note 1) 8 ns/v
74act273 4/11 dc specifications 1) maximum test duration 2ms, one output loaded at time 2) incident wave switching is guaranteed on transmission lines with impedances as low as 50 w ac electrical characteristics (c l = 50 pf, r l = 500 w , input t r = t f = 3ns) (*) voltage range is 5.0v 0.5v symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. v ih high level input voltage 4.5 v o = 0.1 v or v cc -0.1v 2.0 1.5 2.0 2.0 v 5.5 2.0 1.5 2.0 2.0 v il low level input voltage 4.5 v o = 0.1 v or v cc -0.1v 1.5 0.8 0.8 0.8 5.5 1.5 0.8 0.8 0.8 v v oh high level output voltage 4.5 i o =-50 m a 4.4 4.49 4.4 4.4 5.5 i o =-50 m a 5.4 5.49 5.4 5.4 4.5 i o =-24 ma 3.86 3.76 3.7 v 5.5 i o =-24 ma 4.86 4.76 4.7 v ol low level output voltage 4.5 i o =50 m a 0.001 0.1 0.1 0.1 5.5 i o =50 m a 0.001 0.1 0.1 0.1 4.5 i o =24 ma 0.36 0.44 0.5 5.5 i o =24 ma 0.36 0.44 0.5 i i input leakage cur- rent 5.5 v i = v cc or gnd 0.1 1 1 m a i cct max i cc /input 5.5 v i = v cc - 2.1v 0.6 1.5 1.6 ma i cc quiescent supply current 5.5 v i = v cc or gnd 44080 m a i old dynamic output current (note 1, 2) 5.5 v old = 1.65 v max 75 50 ma i ohd v ohd = 3.85 v min -75 -50 ma symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. t plh t phl propagation delay time clock to y 5.0 (*) 1.5 4.0 8.5 1.5 9.0 1.5 9.0 ns t phl propagation delay time clear to y 5.0 (*) 1.5 4.5 9.0 1.5 9.5 1.5 9.5 ns t wl clear pulse width 5.0 (*) 2.3 4.0 4.0 4.0 ns t w clock pulse width 5.0 (*) 1.8 4.0 4.0 4.0 ns t s setup time d to clock, high or low 5.0 (*) 1.0 3.5 3.5 3.5 ns t h hold time d to clock, high or low 5.0 (*) -0.5 1.5 1.5 1.5 ns t rem recovery time clear to clock 5.0 (*) 0.5 3.0 3.0 3.0 ns f max maximum clock frequency 5.0 (*) 125 190 110 110 mhz
74act273 5/11 capacitive characteristics 1) c pd is defined as the value of the ics internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) = c pd x v cc x f in + i cc /n (per circuit) test circuit c l = 50pf or equivalent (includes jig and probe capacitance) r l = r 1 = 500 w or equivalent r t = z out of pulse generator (typically 50 w) symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. c in input capacitance 5.0 4 pf c pd power dissipation capacitance (note 1) 5.0 f in = 10mhz 32 pf
74act273 6/11 waveform 1: propagation delays, setup and hold times (f=1mhz; 50% duty cycle) waveform 2: propagation delays (f=1mhz; 50% duty cycle)
74act273 7/11 waveform 3: recovery time (f=1mhz; 50% duty cycle)
74act273 8/11 dim. mm inch min. typ. max. min. typ. max. a1 0.254 0.010 b 1.39 1.65 0.055 0.065 b0.45 0.018 b1 0.25 0.010 d 25.4 1.000 e8.5 0.335 e2.54 0.100 e3 22.86 0.900 f7.10.280 i3.930.155 l3.3 0.130 z1.340.053 p001j plastic dip-20 (0.25) mechanical data
74act273 9/11 dim. mm inch min. typ. max. min. typ. max. a2.650.104 a1 0.10 0.20 0.004 0.007 a2 2.45 0.096 b 0.35 0.49 0.013 0.019 b1 0.23 0.32 0.009 0.012 c0.50 0.020 c1 45 (typ.) d 12.60 13.00 0.496 0.512 e 10.00 10.65 0.393 0.419 e1.27 0.050 e3 11.43 0.450 f 7.40 7.60 0.291 0.299 l 0.50 1.27 0.19 0.050 m0.750.029 s8 (max.) p013l so-20 mechanical data
74act273 10/11 dim. mm inch min. typ. max. min. typ. max. a1.10.433 a1 0.05 0.10 0.15 0.002 0.004 0.006 a2 0.85 0.9 0.95 0.335 0.354 0.374 b 0.19 0.30 0.0075 0.0118 c 0.09 0.2 0.0035 0.0079 d 6.4 6.5 6.6 0.252 0.256 0.260 e 6.25 6.4 6.5 0.246 0.252 0.256 e1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 bsc 0.0256 bsc k0 o 4 o 8 o 0 o 4 o 8 o l 0.50 0.60 0.70 0.020 0.024 0.028 c e b a2 a e1 d 1 pin 1 identification a1 l k e tssop20 mechanical data
74act273 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco singapore - spain - sweden - switzerland - united kingdom ? http://www.st.com 11/11

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